<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>COSP -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">COSP</h2>
      <p class="aml">Clear Other Speculative Predictions by Context prevents predictions, other than Cache prefetch, Control flow, and Data Value predictions, that predict execution addresses based on information gathered from earlier execution within a particular execution context. Predictions, other than Cache prefetch, Control flow, and Data Value predictions, determined by the actions of code in the target execution context or contexts appearing in program order before the instruction cannot exploitatively control any speculative access occurring after the instruction is complete and synchronized.</p>
    <p>
        This is an alias of
        <a href="sys.html">SYS</a>.
        This means:
      </p><ul><li>
          The encodings in this description are named to match the encodings of
          <a href="sys.html">SYS</a>.
        </li><li>The description of <a href="sys.html">SYS</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul>
    <h3 class="classheading"><a id="iclass_system"/>System<span style="font-size:smaller;"><br/>(FEAT_SPECRES2)
          </span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td>1</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>1</td><td class="r">1</td><td class="l">1</td><td>1</td><td class="r">0</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td colspan="10"/><td class="droppedname">L</td><td colspan="2"/><td colspan="3" class="droppedname">op1</td><td colspan="4" class="droppedname">CRn</td><td colspan="4" class="droppedname">CRm</td><td colspan="3" class="droppedname">op2</td><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="COSP_SYS_CR_systeminstrs"/><p class="asm-code">COSP  RCTX, <a href="#sa_xt_1" title="64-bit general-purpose source register (field &quot;Rt&quot;)">&lt;Xt&gt;</a></p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="sys.html#SYS_CR_systeminstrs">SYS</a> #3, C7, C3, #6, <a href="#sa_xt_1" title="64-bit general-purpose source register (field &quot;Rt&quot;)">&lt;Xt&gt;</a></p>
          <p class="equivto">
          and is always the preferred disassembly.
        </p>
        </div>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xt&gt;</td><td><a id="sa_xt_1"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose source register, encoded in the "Rt" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="sys.html">SYS</a> gives the operational pseudocode for this instruction.</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
    </p></body></html>
